For example, a non-isolated DC/DC converter used in power source circuit for a desktop PC, a notebook PC, a game machine, or the like is in a trend of large current use and high frequency use according to demand for large current use in a CPU (Central Processing Unit) or an MPU (Micro Processing Unit) or demand for size reduction of a choke coil or an input/output capacitor which is a passive part. The DC/DC converter is composed of a high-side switch and a low-side switch, where a power MOSFET is used in each of the switches.
The switches are alternately turned ON/OFF to perform voltage conversion while synchronizing the high-side and low-side switches with each other. The high-side switch is a switch for controlling the DC/DC converter and the low-side switch is a switch for synchronization and rectification.
A recent DC/DC converter is in a trend for advance to the system-in-package obtained by packaging a high-side switch, a low-side switch, and a driver IC for driving the switches in one package in order to reduce parasitic inductances among chips and satisfy high-speed response and size reduction.
FIG. 10 is a circuit diagram of a DC/DC converter using a conventional system-in-package. A system-in-package 1 comprises a high-side MOSFET 2, a low-side MOSFET 3, and pre-drivers 4 and 5 which drive the respective MOSFETs. Here, the pre-drivers 4 and 5 are formed in a driver IC 6 as one chip, and three chips of the high-side MOSFET 2, the low-side MOSFET 3, and the driver IC 6 are mounted in one package.
An operation principle and respective constituent elements of a DC/DC converter using the system-in-package will be explained. The pre-drivers 4 and 5 drive gates of the high-side MOSFET 2 and the low-side MOSFET 3 via wires 7 and 9 according to input of a PWM signal from a PWM controller 11. Source potentials of the high-side MOSFET 2 and the low-side MOSFET 3 are inputted to the pre-drivers 4 and 5 via wires 8 and 10, and respective gate voltages thereof are applied based upon the source potentials. A voltage (VIN) applied to an input terminal 25 via an input capacitor 14 is converted to a desired voltage according to a ratio of an ON period between the high-side MOSFET 2 and the low-side MOSFET 3 to be outputted to an output terminal 26. The outputted voltage is smoothed by a choke coil 13 and an output capacitor 12 so that an output voltage (VOUT) is outputted. A power ground terminal 27 connected to a power ground 29 and a logic ground terminal 28 connected to a logic ground 30 are provided, respectively.
FIG. 11 is a diagram showing a configuration example of a system-in-package for the conventional DC/DC converter (for example, see Japanese Patent Application Laid-Open Publication No. 2004-342735 (Patent Document 1)). As the package, a QFN (Quad Flat Non-leaded package) is used, which is one of non-leaded surface-mounted packages. A tub of the package is divided to three tabs 15, 16, and 17. The high-side MOSFET 2, the low-side MOSFET 3, and the driver IC 6 are mounted on these tabs, respectively. Source pads 18 and a gate pad 19 are provided on the high-side MOSFET 2 and they are connected to the driver IC 6 via wires 7 and 8. The high-side MOSFET 2 is connected to the low-side MOSFET 3 via a wire 23 and the tab 16. Source pads 20 and 22, and a gate pad 21 are provided on the low-side MOSFET 3, and the low-side MOSFET 3 is connected to the driver IC 6 via wires 9 and 10. The low-side MOSFET 3 is connected to a power ground terminal 27 via wires 24. The tab 17 mounted with the driver IC 6 is connected to a logic ground 30 via logic ground terminals 28.
Next, influence of parasitic inductance in a main circuit will be explained. FIG. 12 is a circuit diagram showing a portion of circuit configuration of the conventional DC/DC converter, where L1 to L6 denote parasitic inductances in a main circuit. Here, L1 represents a parasitic inductance between an input power source (Vin) and a drain of the high-side MOSFET 2, namely, the sum of a wire inductance of a portion of a printed circuit board extending from the input capacitor 14 to the input terminal 25 of the system-in-package and a parasitic inductance of the tub 15 mounted with the high-side MOSFET 3. L2 represents a parasitic inductance between the source of the high-side MOSFET 2 and a reference potential of the pre-driver 4, namely, a parasitic inductance of the source electrode of the high-side MOSFET 2. L3 represents a parasitic inductance between the source of the high-side MOSFET 2 and the output terminal 26, namely, a parasitic inductance of a wire (wire 23) of the source of the high-side MOSFET 2. L4 represents a parasitic inductance between the output terminal 26 and a drain of a low-side MOSFET 3, namely, a parasitic inductance of the tab 16 mounted with the low-side MOSFET 3. L5 represents a parasitic inductance between a source of the low-side MOSFET 3 and a reference potential of the pre-driver 5, namely, a parasitic inductance of the source electrode of the low-side MOSFET 3. L6 represents a parasitic inductance between the source of the low-side MOSFET 3 and a power ground 29, namely, the sum of a parasitic inductance of a wire (wire 24) of the source of the low-side MOSFET 3 and a wire inductance of a portion of the printed circuit board extending from a power ground terminal 27 of the system-in-package 1 to the input capacitor 14.
Conventionally, it is known that reduction of the sum (L1+L2+ . . . L6) of inductances in the main circuit or reduction of the parasitic inductance L2 between the high-side MOSFET 2 and the reference potential of the pre-driver 4 is effective for reduction of loss in the DC/DC converter.
In the system-in-package, since the high-side MOSFET 2 and the low-side MOSFET 3 are packaged in one package, the sum of the inductances in the main circuit can be reduced, and since the reference potential of the pre-driver 4 is applied from the source electrode of the high-side MOSFET 2 via a wire (wire 8), L2 eventually contains only the parasitic inductance of the source electrode so that L2 can be reduced considerably.
However, such a problem as a self turn-on phenomenon occurs in the DC/DC converter. The self turn-on phenomenon means a phenomenon that, when the high-side MOSFET is turned ON in an OFF state of the low-side MOSFET, a drain voltage of the low-side MOSFET rises, a charging current flows between the gate and the source of the low-side MOSFET via a feedback capacity between the gate and the drain of the low-side MOSFET according to the voltage change, and a gate voltage of the low-side MOSFET rises to exceed a threshold voltage, thereby causing erroneous turn-on of the low-side MOSFET.
FIG. 13 is a graph showing a calculation result of a voltage Vgs between the gate and the source of the low-side MOSFET. As shown in FIG. 13, it is understood that, after the low-side MOSFET is turned OFF, the gate voltage of the low-side MOSFET rises according to turning-ON of the high-side MOSFET. When the self turn-on phenomenon occurs, a large feed-through current flows from the high-side MOSFET to the low-side MOSFET so that conversion efficiency lowers largely. As an actual low-side MOSFET, a MOSFET having a high threshold voltage to a certain extent must be used so as not to cause the self turn-on phenomenon, which results in such a problem that high efficiency can not be achieved due to increase in conduction loss.
As a technique for preventing the self turn-on phenomenon, a technique where, even if a gate voltage of a low-side switch rises, the gate voltage does not exceeds a threshold voltage to be capable of preventing the self turn-on by driving the gate voltage of the low-side switch at a negative potential has been proposed, for example, in Japanese Patent Application Laid-Open Publication No. 2004-15974 (Patent Document 2). A technique where an auxiliary switch is provided between a gate and a source of a low-side MOSFET and the gate and the source are short-circuited to prevent rising of a gate voltage by making the auxiliary switch conductive at a rising time of a gate voltage of a low-side switch has been proposed in Japanese patent Application laid-Open Publication No. 2002-290224 (Patent Document 3).